1. Field of the Invention
The present invention is related to high-speed communications of data in a communication system and, in particular, to high data rate transmission of data between components in a communication system.
2. Discussion of Related Art
There is currently a great deal of interest in high speed transceiver systems, both for communications in an intranet environment and for communications between components in various systems. As an example of a high data rate system, high-speed Ethernet local area networks (LANs), 100 BASE-TX Ethernet and 1000 Base TX Ethernet (1 Gigabit/s) using category-5, 5E or 6 copper wire, are being developed. These high speed systems require new techniques in high-speed data processing. High-speed data transmission techniques are also useful in wide-area networks and digital subscriber loop applications. High data rate transceiver systems are also utilized in many back-plane environments, including optical switching devices, router systems, switches, and storage area networking switches. Other environments that utilize high speed communication between components include inter-cabinet communications and chip-to-chip communications.
Typically, data is transferred in a communication system by transmitting signals having voltages from sets of voltages referred to as symbol sets. Each symbol (i.e. voltage level) in the symbol set represents one or more digital bits of data. Existing techniques utilized in such environments typically use non-return to zero (NRZ) modulation to send and receive information over high-bandwidth transmission media. Other common symbol sets include MLT3, PAM or QAM systems. Typically, the transceiver for sending high-speed data over such networks is called a serializer/deserializer, or SERDES, device.
FIG. 1A shows a block diagram of a typical transceiver environment 100. Components 101-1 through 101-Q are coupled to transmit and receive data through input/output (I/O) ports 102-1 through 102-Q, respectively, which are coupled through transmission medium 110. Conventionally, components 101-1 through 101-Q are SERDES devices. Transceiver environment 100 can represent either a back-plane environment (where components 101-1 through 101-Q are physically relatively close to one another) or a networking environment (where components 101-1 through 101-Q are more separated).
FIG. 1B shows a block diagram of a conventional transmitter portion of one of SERDES devices 101-1 through 101-Q on I/O ports 102-1 through 102-Q, respectively. Parallel data is received in a bit encoder 105. Bit encoder 105 encodes the parallel data, for example by adding redundancy in the input data, to ensure a minimum rate of data transitions in the output data stream. Typical encoding schemes include rate 8/10 (8 bit input to 10 bit output) encoding. The parallel data is serialized in parallel to serial converter 106. Output driver 107 then receives the serialized data from parallel to serial converter 106 and outputs, usually, a differential voltage signal for transmission over transmission medium 110. In addition, there is typically a phase locked loop (PLL) 114 that provides the necessary clock signals for encoder 105 and parallel-to-serial converter 106. The input signal to PLL 114 is a reference clock signal from a system PLL 103.
FIG. 1C shows an example of a conventional receiver 108 of one of SERDES devices 101-1 through 101-Q on I/O ports 102-1 through 102-Q, respectively, of FIG. 1A. Input driver 109 receives a differential voltage signal from transmission medium 110 and outputs the analog data signal to clock and data recovery circuit 115. Data recovery 115 can, in some systems, perform equalization, recover the timing, and output a serial bit stream of data to serial-to-parallel converter 111. The serial data is input to bit decoder 112, which converts the parallel data to parallel decoded data. Clock and data recovery circuit 115 also outputs the necessary clock signals to serial-to-parallel converter 111 and bit decoder 112.
The actual demands for the various data transmission environments may vary widely (e.g., LAN environments have different transmission requirements from back-plane environments). A conventional SERDES system 100 for a back-plane environment, for example, can enable serial data communication at data rates as high as 2.5 Gbps to 3.125 Gbps over a pair of FR4 copper traces in a copper back-plane communication system. Current systems utilizing category 5, 5E or 6 copper wire can enable serial data communications rates as high as 1 Gbit/sec using Gigabit Ethernet. One of the biggest problems with existing SERDES systems 100 is that they are very bandwidth inefficient, i.e., they require 3.125 GHz of bandwidth to transmit and receive 2.5 Gbps of data over a single pair of copper wires. Therefore, it is very difficult to increase the data rates across bus 110. Additionally, SERDES system 100 requires the implementation of a high clock rate (3.125 GHz for 2.5 Gbps data rates) phase locked loop (PLL) 114 implemented to transmit data and recover high clock rates in data recovery 115. The timing window within which receiver 108 needs to determine whether the received symbol in data recovery 115 is a 1 or a 0 is about 320 ps for the higher data rate systems. This timing window creates extremely stringent requirements on the design of data recovery 115 and PLL 114, as they must have very low peak-to-peak jitter.
Conventional networking environments operate at slower baud rates, but suffer from similar difficulties. As an example, a 1 Gigabit transfer can be accomplished through transmitting PAM-5 data at 125 MHz through four (4) twisted copper pair. It would be desirable to allow higher data rates in networking environments.
Conventional SERDES system 100 also suffers from other problems, including eye closure due to intersymbol interference (ISI) from the dispersion introduced by transmission medium 110. The ISI is a direct result of the fact that the copper traces of transmission medium 110 attenuate higher frequency components in the transmitted signals more than the lower frequency components in the transmitted signals. Therefore, the higher the data rate the more ISI suffered by the transmitted data. In addition, electrical connectors and electrical connections (e.g., vias and other components) used in SERDES device 100 cause reflections, which also cause ISI.
To overcome these problems, equalization must be performed on the received signal in data recovery 115. However, in existing very high data-rate communication systems, equalization is very difficult to perform, if not impossible due to the high baud rate. A more commonly utilized technique for combating ISI is known as “pre-emphasis”, or pre-equalization, performed in bit encoder 105 and output driver 107 during transmission. In some conventional systems, the amplitude of the low-frequencies in the transmitted signal is attenuated to compensate for the higher attenuation of the high frequency component by the transmission medium of bus 110. While this makes the receiver more robust to ISI, pre-emphasis reduces the overall noise tolerance of transmission over transmission medium 110 of communication system 100 due to the loss of signal-to-noise ratio (SNR). At higher data rates, conventional systems quickly become intractable due to the increased demands.
Another difficulty with conventional SERDES system 100 is with correction for near-end cross talk (NEXT) interference, Far-end cross talk interference (FEXT) and echo cancellation. NEXT interference relates to the interference between the transmitter portions of device 101-q, an arbitrary one of devices 101-1 through 101-Q, and the receiver portions of device 101-q, where the interfering transmitter portion is transmitting on a separate conductor from the receiver portion. Echo refers to the interference between the transmitter portions of device 101-q and the receiver portions of device 101-q, where the transmitter portion is transmitting on the same wire as the receiver portion. FEXT refers to interference between transmitters of counterpart transmitter portions transmitting to the receiver portion of device 101-q. In many cases, transmitter 104 and receiver 108 of device 101-q are adjacently located as transceiver SERDES device 101-1 and may share a bus line to bus 110. Further, in many cases device 101-q is in communication with one or more counterpart ones of devices 101-1 through 101-Q that can provide interference to the receiver portion of device 101-q. For example, NEXT, FEXT and Echo interference can be problematic in systems utilizing category 5, 5E or 6 cabling, which are capable of supporting high transmission rates.
Therefore, there is a need for a more robust system for transmitting data in a transmission system at very high speeds.